McqMate
| 401. |
For programmable logic functions, which type of PLD should be used? |
| A. | pla |
| B. | pal |
| C. | cpld |
| D. | sld |
| Answer» B. pal | |
| 402. |
The complex programmable logic device contains several PLD blocks and |
| A. | a language compiler |
| B. | and/or arrays |
| C. | global interconnection matrix |
| D. | field-programmable switches |
| Answer» C. global interconnection matrix | |
| 403. |
Which type of device FPGA are? |
| A. | sld |
| B. | srom |
| C. | eprom |
| D. | pld |
| Answer» D. pld | |
| 404. |
The difference between a PAL & a PLA is |
| A. | pals and plas are the same thing |
| B. | the pla has a programmable or plane and a programmable and plane, while the pal only has a programmable and plane |
| C. | the pal has a programmable or plane and a programmable and plane, while the pla only has a programmable and plane |
| D. | the pal has more possible product terms than the pla |
| Answer» B. the pla has a programmable or plane and a programmable and plane, while the pal only has a programmable and plane | |
| 405. |
If a PAL has been programmed once |
| A. | its logic capacity is lost |
| B. | its outputs are only active high |
| C. | its outputs are only active low |
| D. | it cannot be reprogrammed |
| Answer» D. it cannot be reprogrammed | |
| 406. |
The FPGA refers to |
| A. | first programmable gate array |
| B. | field programmable gate array |
| C. | first program gate array |
| D. | field program gate array |
| Answer» B. field programmable gate array | |
| 407. |
The full form of VLSI is |
| A. | very long single integration |
| B. | very least scale integration |
| C. | very large scale integration |
| D. | very long scale integration |
| Answer» C. very large scale integration | |
| 408. |
In FPGA, vertical and horizontal directions are separated by |
| A. | a line |
| B. | a channel |
| C. | a strobe |
| D. | a flip-flop |
| Answer» B. a channel | |
| 409. |
Applications of PLAs are |
| A. | registered pals |
| B. | configurable pals |
| C. | pal programming |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| 410. |
CMOS refers to |
| A. | continuous metal oxide semiconductor |
| B. | complementary metal oxide semiconductor |
| C. | centred metal oxide semiconductor |
| D. | concrete metal oxide semiconductor |
| Answer» B. complementary metal oxide semiconductor | |
| 411. |
Propagation delay is defined as |
| A. | the time taken for the output of a gate to change after the inputs have changed |
| B. | the time taken for the input of a gate to change after the outputs have changed |
| C. | the time taken for the input of a gate to change after the intermediates have changed |
| D. | the time taken for the output of a gate to change after the intermediates have changed |
| Answer» A. the time taken for the output of a gate to change after the inputs have changed | |
| 412. |
Propagation delay times can be divided as |
| A. | t(plh) and t(lph) |
| B. | t(lph) and t(phl) |
| C. | t(plh) and t(phl) |
| D. | t(hpl) and t(lph) |
| Answer» C. t(plh) and t(phl) | |
| 413. |
Power Dissipation in DIC is expressed in |
| A. | watts or kilowatts |
| B. | milliwatts or nanowatts |
| C. | db |
| D. | mdb |
| Answer» B. milliwatts or nanowatts | |
| 414. |
Fan-in is defined as |
| A. | the number of outputs connected to gate without any degradation in the voltage levels |
| B. | the number of inputs connected to gate without any degradation in the voltage levels |
| C. | the number of outputs connected to gate with degradation in the voltage levels |
| D. | the number of inputs connected to gate with degradation in the voltage levels |
| Answer» B. the number of inputs connected to gate without any degradation in the voltage levels | |
| 415. |
The maximum noise voltage that may appear at the input of a logic gate without changing the logical state of its output is termed as |
| A. | noise margin |
| B. | noise immunity |
| C. | white noise |
| D. | signal to noise ratio |
| Answer» B. noise immunity | |
| 416. |
The full form of ECL is |
| A. | emitter-collector logic |
| B. | emitter-complementary logic |
| C. | emitter-coupled logic |
| D. | emitter-cored logic |
| Answer» C. emitter-coupled logic | |
| 417. |
Which logic is the fastest of all the logic families? |
| A. | ttl |
| B. | ecl |
| C. | htl |
| D. | dtl |
| Answer» B. ecl | |
| 418. |
The full form of CML is |
| A. | complementary mode logic |
| B. | current mode logic |
| C. | collector mode logic |
| D. | collector mixed logic |
| Answer» C. collector mode logic | |
| 419. |
In an ECL the output is taken from |
| A. | emitter |
| B. | base |
| C. | collector |
| D. | junction of emitter and base |
| Answer» C. collector | |
| 420. |
The ECL behaves as |
| A. | not gate |
| B. | nor gate |
| C. | nand gate |
| D. | and gate |
| Answer» B. nor gate | |
| 421. |
In ECL the fanout capability is |
| A. | high |
| B. | low |
| C. | zero |
| D. | sometimes high and sometimes low |
| Answer» A. high | |
| 422. |
ECL’s major disadvantage is that |
| A. | it requires more power |
| B. | it’s fanout capability is high |
| C. | it creates more noise |
| D. | it is slow |
| Answer» A. it requires more power | |
| 423. |
The full form of SCFL is |
| A. | source-collector logic |
| B. | source-coupled logic |
| C. | source-complementary logic |
| D. | source cored logic |
| Answer» B. source-coupled logic | |
| 424. |
The equivalent of emitter-coupled logic made out of FETs is called |
| A. | cml |
| B. | scfl |
| C. | fecl |
| D. | efcl |
| Answer» B. scfl | |
| 425. |
ECL was invented in by |
| A. | 1956, baker clamp |
| B. | 1976, james r. biard |
| C. | 1956, hannon s. yourke |
| D. | 1976, yourke |
| Answer» C. 1956, hannon s. yourke | |
| 426. |
At the time of invention, an ECL was called as |
| A. | source-coupled logic |
| B. | current mode logic |
| C. | current-steering logic |
| D. | emitter-coupled logic |
| Answer» C. current-steering logic | |
| 427. |
The ECL circuits usually operates with |
| A. | negative voltage |
| B. | positive voltage |
| C. | grounded voltage |
| D. | high voltage |
| Answer» A. negative voltage | |
| 428. |
Low-voltage positive emitter-coupled logic (LVPECL) is a power optimized version of |
| A. | ecl |
| B. | vecl |
| C. | pecl |
| D. | lecl |
| Answer» C. pecl | |
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