420+ Digital Electronics Solved MCQs

These multiple-choice questions (MCQs) are designed to enhance your knowledge and understanding in the following areas: Electrical Engineering , Bachelor of Science in Computer Science FY (BSc CS) , Bachelor of Computer Applications (BCA) , Bachelor of Science in Computer Science (BSc CS) .

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251.	Non inverting dynamic register storage cell consists of transistors for nMOS and for CMOS.
A.	six, eight
B.	eight, six
C.	five, six
D.	six, five
Answer» A. six, eight

252.	Register cell consists of
A.	inverter
B.	pass transistor
C.	inverter & pass transistor
D.	none of the mentioned
Answer» C. inverter & pass transistor

253.	In a four bit dynamic shift register basic nMOS transistor or inverters are connected in
A.	series
B.	cascade
C.	parallel
D.	series and parallel
Answer» B. cascade

254.	In four bit dynamic shift register output is obtained
A.	parallel output at inverters 1, 3, 5, 7
B.	parallel output at inverters 1, 5, 8
C.	parallel output at all inverters
D.	parallel output at inverter 2, 4, 6, 8
Answer» D. parallel output at inverter 2, 4, 6, 8

255.	Output values of Moore type FSM are determined by its
A.	input values
B.	output values
C.	clock input
D.	current state
Answer» D. current state

256.	Moore machine output is synchronous.
A.	true
B.	false
Answer» A. true

257.	Finite state machines are combinational logic systems.
A.	true
B.	false
Answer» B. false

258.	What happens if the input is high in FSM?
A.	change of state
B.	no transition in state
C.	remains in a single state
D.	invalid state
Answer» A. change of state

259.	What happens if the input is low in FSM?
A.	change of state
B.	no transition in state
C.	remains in a single state
D.	invalid state
Answer» B. no transition in state

260.	In FSM diagram what does circle represent?
A.	change of state
B.	state
C.	output value
D.	initial state
Answer» B. state

261.	In the FSM diagram, what does arrow between the circles represent?
A.	change of state
B.	state
C.	output value
D.	initial state
Answer» A. change of state

263.	Moore machine has states than a mealy machine.
A.	fewer
B.	more
C.	equal
D.	negligible
Answer» B. more

264.	State transition happens in every clock cycle.
A.	once
B.	twice
C.	thrice
D.	four times
Answer» A. once

265.	In digital logic, a counter is a device which
A.	counts the number of outputs
B.	stores the number of times a particular event or process has occurred
C.	stores the number of times a clock pulse rises and falls
D.	counts the number of inputs
Answer» B. stores the number of times a particular event or process has occurred

266.	A counter circuit is usually constructed of
A.	a number of latches connected in cascade form
B.	a number of nand gates connected in cascade form
C.	a number of flip-flops connected in cascade
D.	a number of nor gates connected in cascade form
Answer» C. a number of flip-flops connected in cascade

262.	In the FSM diagram, what does the information below the line in the circle represent?
A.	change of state
B.	state
C.	output value
D.	initial state
Answer» C. output value

267.	A decimal counter has states.
A.	5
B.	10
C.	15
D.	20
Answer» B. 10

268.	What is the maximum possible range of bit-count specifically in n-bit binary counter consisting of ‘n’ number of flip-flops?
A.	0 to 2n
B.	0 to 2n + 1
C.	0 to 2n – 1
D.	0 to 2n+1/2
Answer» C. 0 to 2n – 1

269.	How many types of the counter are there?
A.	2
B.	3
C.	4
D.	5
Answer» B. 3

270.	Three decade counter would have
A.	2 bcd counters
B.	3 bcd counters
C.	4 bcd counters
D.	5 bcd counters
Answer» B. 3 bcd counters

271.	BCD counter is also known as
A.	parallel counter
B.	decade counter
C.	synchronous counter
D.	vlsi counter
Answer» B. decade counter

272.	The parallel outputs of a counter circuit represent the
A.	parallel data word
B.	clock frequency
C.	counter modulus
D.	clock count
Answer» D. clock count

273.	Ring shift and Johnson counters are
A.	synchronous counters
B.	asynchronous counters
C.	true binary counters
D.	synchronous and true binary counters
Answer» A. synchronous counters

274.	What is the difference between a shift-right register and a shift-left register?
A.	there is no difference
B.	the direction of the shift
C.	propagation delay
D.	the clock input
Answer» B. the direction of the shift

275.	What is a transceiver circuit?
A.	a buffer that transfers data from input to output
B.	a buffer that transfers data from output to input
C.	a buffer that can operate in both directions
D.	a buffer that can operate in one direction
Answer» C. a buffer that can operate in both directions

420+ Digital Electronics Solved MCQs

Non inverting dynamic register storage cell consists of transistors for nMOS and for CMOS.

Register cell consists of

In a four bit dynamic shift register basic nMOS transistor or inverters are connected in

In four bit dynamic shift register output is obtained

Output values of Moore type FSM are determined by its

Moore machine output is synchronous.

Finite state machines are combinational logic systems.

What happens if the input is high in FSM?

What happens if the input is low in FSM?

In FSM diagram what does circle represent?

In the FSM diagram, what does arrow between the circles represent?

In the FSM diagram, what does the information below the line in the circle represent?

Moore machine has states than a mealy machine.

State transition happens in every clock cycle.

In digital logic, a counter is a device which

A counter circuit is usually constructed of

A decimal counter has states.

What is the maximum possible range of bit-count specifically in n-bit binary counter consisting of ‘n’ number of flip-flops?

How many types of the counter are there?

Three decade counter would have

BCD counter is also known as

The parallel outputs of a counter circuit represent the

Ring shift and Johnson counters are

What is the difference between a shift-right register and a shift-left register?

What is a transceiver circuit?

A 74HC195 4-bit parallel access shift register can be used for

What is the function of a buffer circuit?

What is the preset condition for a ring shift counter?

Another way to connect devices to a shared data bus is to use a

The full form of SIPO is

A shift register that will accept a parallel input or a bidirectional serial load and internal shift features is called as?

How can parallel data be taken out of a shift register simultaneously?

What is meant by parallel load of a shift register?

The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains

Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first)

A serial in/parallel out, 4-bit shift register initially contains all 1s. The data nibble 0111 is waiting to enter. After four clock pulses, the register contains

With a 200 kHz clock frequency, eight bits can be serially entered into a shift register in

An 8-bit serial in/serial out shift register is used with a clock frequency of 2 MHz to achieve a time delay (td) of

A sequence of equally spaced timing pulses may be easily generated by which type of counter circuit?

A bidirectional 4-bit shift register is storing the nibble 1101. Its input is HIGH. The nibble 1011 is waiting to be entered on the serial data-input line. After three clock pulses, the shift register is storing

How many clock pulses will be required to completely load serially a 5-bit shift register?

How is an strobe signal used when serially loading a shift register?

An 8-bit serial in/serial out shift register is used with a clock frequency of 150 kHz. What is the time delay between the serial input and the Q3 output?

What are the three output conditions of a three-state buffer?

The primary purpose of a three-state buffer is usually

What is the difference between a ring shift counter and a Johnson shift counter?

A latch is an example of a

Latch is a device with

Why latches are called a memory devices?

Two stable states of latches are

276.	A 74HC195 4-bit parallel access shift register can be used for
A.	serial in/serial out operation
B.	serial in/parallel out operation
C.	parallel in/serial out operation
D.	all of the mentioned
Answer» D. all of the mentioned

277.	What is the function of a buffer circuit?
A.	to provide an output that is inverted from that on the input
B.	to provide an output that is equal to its input
C.	to clean up the input
D.	to clean up the output
Answer» B. to provide an output that is equal to its input

278.	What is the preset condition for a ring shift counter?
A.	all ffs set to 1
B.	all ffs cleared to 0
C.	a single 0, the rest 1
D.	a single 1, the rest 0
Answer» D. a single 1, the rest 0

279.	Another way to connect devices to a shared data bus is to use a
A.	circulating gate
B.	transceiver
C.	bidirectional encoder
D.	strobed latch
Answer» B. transceiver

280.	The full form of SIPO is
A.	serial-in parallel-out
B.	parallel-in serial-out
C.	serial-in serial-out
D.	serial-in peripheral-out
Answer» A. serial-in parallel-out

281.	A shift register that will accept a parallel input or a bidirectional serial load and internal shift features is called as?
A.	tristate
B.	end around
C.	universal
D.	conversion
Answer» C. universal

282.	How can parallel data be taken out of a shift register simultaneously?
A.	use the q output of the first ff
B.	use the q output of the last ff
C.	tie all of the q outputs together
D.	use the q output of each ff
Answer» D. use the q output of each ff

283.	What is meant by parallel load of a shift register?
A.	all ffs are preset with data
B.	each ff is loaded with data, one at a time
C.	parallel shifting of data
D.	all ffs are set with data
Answer» A. all ffs are preset with data

284.	The group of bits 11001 is serially shifted (right-most bit first) into a 5-bit parallel output shift register with an initial state 01110. After three clock pulses, the register contains
A.	01110
B.	00001
C.	00101
D.	00110
Answer» C. 00101

285.	Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first)
A.	1100
B.	0011
C.	0000
D.	1111
Answer» C. 0000