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301. |
Which of the following flip-flop is used by the ring counter? |
A. | d flip-flops |
B. | sr flip-flops |
C. | jk flip-flops |
D. | t flip-flops |
Answer» A. d flip-flops |
302. |
‘shift_reg’ is used to initialize the |
A. | lsb |
B. | msb |
C. | register type |
D. | register bits |
Answer» B. msb |
303. |
How many types of shift operators are there in VHDL? |
A. | three |
B. | four |
C. | five |
D. | six |
Answer» D. six |
304. |
How many types of the data type are there in the ring counter? |
A. | one |
B. | two |
C. | three |
D. | more than three |
Answer» D. more than three |
305. |
In counter universal clock is not used. |
A. | synchronous counter |
B. | asynchronous counter |
C. | decade counter |
D. | ring counter |
Answer» B. asynchronous counter |
306. |
Synchronous counter use global clock, unlike asynchronous counter. |
A. | one |
B. | two |
C. | three |
D. | zero |
Answer» A. one |
307. |
How many different states does a decade counter count? |
A. | eight |
B. | nine |
C. | ten |
D. | eleven |
Answer» C. ten |
308. |
Output values of Moore type FSM are determined by its |
A. | input values |
B. | output values |
C. | clock input |
D. | current state |
Answer» D. current state |
309. |
What happens if the input is high in FSM? |
A. | change of state |
B. | no transition in state |
C. | remains in a single state |
D. | invalid state |
Answer» A. change of state |
310. |
What happens if the input is low in FSM? |
A. | change of state |
B. | no transition in state |
C. | remains in a single state |
D. | invalid state |
Answer» B. no transition in state |
311. |
. In FSM diagram what does circle represent? |
A. | change of state |
B. | state |
C. | output value |
D. | initial state |
Answer» B. state |
312. |
In the FSM diagram, what does arrow between the circles represent? |
A. | change of state |
B. | state |
C. | output value |
D. | initial state |
Answer» A. change of state |
313. |
. In the FSM diagram, what does the information below the line in the circle represent? |
A. | change of state |
B. | state |
C. | output value |
D. | initial state |
Answer» C. output value |
314. |
Moore machine has states than a mealy machine. |
A. | fewer |
B. | more |
C. | equal |
D. | negligible |
Answer» B. more |
315. |
State transition happens in every clock cycle. |
A. | once |
B. | twice |
C. | thrice |
D. | four times |
Answer» A. once |
316. |
Output values of mealy type FSM are determined by its |
A. | input values |
B. | output values |
C. | both input values and current state |
D. | current state |
Answer» C. both input values and current state |
317. |
What kind of output does mealy machine produce? |
A. | asynchronous |
B. | synchronous |
C. | level |
D. | pulsed |
Answer» A. asynchronous |
318. |
States in FSM are represented by |
A. | bits |
B. | bytes |
C. | word |
D. | character |
Answer» A. bits |
319. |
What is the first step in writing the VHDL for an FSM? |
A. | to define the vhdl entity |
B. | naming the entity |
C. | defining the data type |
D. | creating the states |
Answer» A. to define the vhdl entity |
320. |
Which of the following react faster to inputs? |
A. | sequencer |
B. | generators |
C. | mealy machines |
D. | moore machines |
Answer» C. mealy machines |
321. |
What is the first state of FSM? |
A. | wait loop state |
B. | initial state |
C. | output state |
D. | activate pulse state |
Answer» B. initial state |
322. |
Mealy machines have states than Moore machine. |
A. | fewer |
B. | more |
C. | equal |
D. | negligible |
Answer» A. fewer |
323. |
In mealy type FSM, the path is labelled by which of the following? |
A. | inputs |
B. | outputs |
C. | both inputs and outputs |
D. | current state |
Answer» C. both inputs and outputs |
324. |
The process statement used in combinational circuits is called process. |
A. | combinational |
B. | clocked |
C. | unclocked |
D. | sequential |
Answer» A. combinational |
325. |
Why we need to include all the input signals in the sensitivity list of the process? |
A. | to monitor the output continuously |
B. | to monitor the input continuously |
C. | to make the circuit synthesizable by eda tools |
D. | no special purpose |
Answer» B. to monitor the input continuously |
326. |
Shift registers comprise of which flip-flops? |
A. | d flip-flops |
B. | sr flip-flops |
C. | jk flip-flops |
D. | t flip-flops |
Answer» A. d flip-flops |
327. |
In serial input serial output register, the data of is accessed by the circuit. |
A. | last flip-flop |
B. | first flip-flop |
C. | all flip-flops |
D. | no flip-flop |
Answer» B. first flip-flop |
328. |
In PIPO shift register, parallel data can be taken out by |
A. | using the q output of the first flip-flop |
B. | using the q output of the last flip-flop |
C. | using the q output of the second flip-flop |
D. | using the q output of each flip-flop |
Answer» D. using the q output of each flip-flop |
329. |
Four bits shift register enables shift control signal in how many clock pulses? |
A. | two clock pulses |
B. | three clock pulses |
C. | four clock pulses |
D. | five clock pulses |
Answer» C. four clock pulses |
330. |
Time taken by the shift register to transfer the content is called |
A. | clock duration |
B. | bit duration |
C. | word duration |
D. | duration |
Answer» C. word duration |
331. |
Transfer of one bit of information at a time is called |
A. | rotating |
B. | serial transfer |
C. | parallel transfer |
D. | shifting |
Answer» B. serial transfer |
332. |
In gated D latch, which of the following is the input symbol? |
A. | d |
B. | q |
C. | en |
D. | clk |
Answer» A. d |
333. |
Which of the following is true about packages? |
A. | package is collection of libraries |
B. | library is collection of packages |
C. | package is collection of entities |
D. | entity is collection of packages |
Answer» B. library is collection of packages |
334. |
A package may consist of design units. |
A. | 2 |
B. | 3 |
C. | 4 |
D. | 5 |
Answer» A. 2 |
335. |
Any item declared in a package declaration section are visible to |
A. | every design unit |
B. | package body only |
C. | library containing that package |
D. | design unit that use the package |
Answer» D. design unit that use the package |
336. |
Which of the following is not a in-built package in VHDL? |
A. | std_logic_1164 |
B. | textio |
C. | standard |
D. | std |
Answer» D. std |
337. |
Packages increases of the code. |
A. | reusability |
B. | readability |
C. | managing |
D. | resolution |
Answer» A. reusability |
338. |
Which of the following can’t have multiple assignments or drivers? |
A. | std_logic |
B. | integer |
C. | std_ulogic |
D. | bit |
Answer» C. std_ulogic |
339. |
Which of the following is a not a characteristics of combinational circuits? |
A. | the output of combinational circuit depends on present input |
B. | there is no use of clock signal in combinational circuits |
C. | the output of combinational circuit depends on previous output |
D. | there is no storage element in combinational circuit |
Answer» C. the output of combinational circuit depends on previous output |
340. |
Which of the following is not a combinational circuit? |
A. | adder |
B. | code convertor |
C. | multiplexer |
D. | counter |
Answer» D. counter |
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