McqMate
These multiple-choice questions (MCQs) are designed to enhance your knowledge and understanding in the following areas: Computer Science Engineering (CSE) .
| 101. |
A basic S-R flip-flop can be constructed by cross-coupling of which basic logic gates? |
| A. | and or or gates |
| B. | xor or xnor gates |
| C. | nor or nand gates |
| D. | and or nor gates |
| Answer» C. nor or nand gates | |
| 102. |
The logic circuits whose outputs at any instant of time depends only on the present input but also on the past outputs are called |
| A. | combinational circuits |
| B. | sequential circuits |
| C. | latches |
| D. | flip-flops |
| Answer» B. sequential circuits | |
| 103. |
Whose operations are more faster among the following? |
| A. | combinational circuits |
| B. | sequential circuits |
| C. | latches |
| D. | flip-flops |
| Answer» A. combinational circuits | |
| 104. |
How many types of sequential circuits are? |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 5 |
| Answer» A. 2 | |
| 105. |
The sequential circuit is also called |
| A. | flip-flop |
| B. | latch |
| C. | strobe |
| D. | adder |
| Answer» B. latch | |
| 106. |
The basic latch consists of |
| A. | two inverters |
| B. | two comparators |
| C. | two amplifiers |
| D. | two adders |
| Answer» A. two inverters | |
| 107. |
In S-R flip-flop, if Q = 0 the output is said to be |
| A. | set |
| B. | reset |
| C. | previous state |
| D. | current state |
| Answer» B. reset | |
| 108. |
The output of latches will remain in set/reset untill |
| A. | the trigger pulse is given to change the state |
| B. | any pulse given to go into previous state |
| C. | they don’t get any pulse more |
| D. | the pulse is edge-triggered |
| Answer» A. the trigger pulse is given to change the state | |
| 109. |
What is a trigger pulse? |
| A. | a pulse that starts a cycle of operation |
| B. | a pulse that reverses the cycle of operation |
| C. | a pulse that prevents a cycle of operation |
| D. | a pulse that enhances a cycle of operation |
| Answer» A. a pulse that starts a cycle of operation | |
| 110. |
A latch is an example of a |
| A. | monostable multivibrator |
| B. | astable multivibrator |
| C. | bistable multivibrator |
| D. | 555 timer |
| Answer» C. bistable multivibrator | |
| 111. |
Latch is a device with |
| A. | one stable state |
| B. | two stable state |
| C. | three stable state |
| D. | infinite stable states |
| Answer» B. two stable state | |
| 112. |
Why latches are called a memory devices? |
| A. | it has capability to stare 8 bits of data |
| B. | it has internal memory of 4 bit |
| C. | it can store one bit of data |
| D. | it can store infinite amount of data |
| Answer» C. it can store one bit of data | |
| 113. |
Two stable states of latches are |
| A. | astable & monostable |
| B. | low input & high output |
| C. | high output & low output |
| D. | low output & high input |
| Answer» C. high output & low output | |
| 114. |
How many types of latches are __ |
| A. | 4 |
| B. | 3 |
| C. | 2 |
| D. | 5 |
| Answer» A. 4 | |
| 115. |
The full form of SR is |
| A. | system rated |
| B. | set reset |
| C. | set ready |
| D. | set rated |
| Answer» B. set reset | |
| 116. |
The SR latch consists of |
| A. | 1 input |
| B. | 2 inputs |
| C. | 3 inputs |
| D. | 4 inputs |
| Answer» B. 2 inputs | |
| 117. |
The outputs of SR latch are |
| A. | x and y |
| B. | a and b |
| C. | s and r |
| D. | q and q’ |
| Answer» D. q and q’ | |
| 118. |
The first step of analysis procedure of SR latch is to |
| A. | label inputs |
| B. | label outputs |
| C. | label states |
| D. | label tables |
| Answer» B. label outputs | |
| 119. |
The inputs of SR latch are |
| A. | x and y |
| B. | a and b |
| C. | s and r |
| D. | j and k |
| Answer» C. s and r | |
| 120. |
When a high is applied to the Set line of an SR latch, then |
| A. | q output goes high |
| B. | q’ output goes high |
| C. | q output goes low |
| D. | both q and q’ go high |
| Answer» A. q output goes high | |
| 121. |
When both inputs of SR latches are low, the latch |
| A. | q output goes high |
| B. | q’ output goes high |
| C. | it remains in its previously set or reset state |
| D. | it goes to its next set or reset state |
| Answer» C. it remains in its previously set or reset state | |
| 122. |
When both inputs of SR latches are high, the latch goes |
| A. | unstable |
| B. | stable |
| C. | metastable |
| D. | bistable |
| Answer» C. metastable | |
| 123. |
The full form of MOS is |
| A. | metal oxide semiconductor |
| B. | metal oxygen semiconductor |
| C. | metallic oxide semiconductor |
| D. | metallic oxygen semiconductor |
| Answer» A. metal oxide semiconductor | |
| 124. |
What are the types of MOSFET devices available? |
| A. | p-type enhancement type mosfet |
| B. | n-type enhancement type mosfet |
| C. | depletion type mosfet |
| D. | all of the mentioned |
| Answer» D. all of the mentioned | |
| 125. |
Which insulating layer used in the fabrication of MOSFET? |
| A. | aluminium oxide |
| B. | silicon nitride |
| C. | silicon dioxide |
| D. | aluminium nitrate |
| Answer» C. silicon dioxide | |
| 126. |
A technique used to reduce the magnitude of threshold voltage of MOSFET is the |
| A. | use of complementary mosfet |
| B. | use of silicon nitride |
| C. | using thin film technology |
| D. | increasing potential of the channel |
| Answer» B. use of silicon nitride | |
| 127. |
What is used to higher the speed of operation in MOSFET fabrication? |
| A. | ceramic gate |
| B. | silicon dioxide |
| C. | silicon nitride |
| D. | poly silicon gate |
| Answer» D. poly silicon gate | |
| 128. |
Why MOSFET is preferred over BJT in IC components? |
| A. | mosfet has low packing density |
| B. | mosfet has medium packing density |
| C. | mosfet has high packing density |
| D. | mosfet has no packing density |
| Answer» A. mosfet has low packing density | |
| 129. |
Critical defects per unit chip area is for a MOS transistor. |
| A. | high |
| B. | low |
| C. | neutral |
| D. | very high |
| Answer» B. low | |
| 130. |
MOS is being used in |
| A. | lsi |
| B. | vlsi |
| C. | msi |
| D. | both lsi and vlsi |
| Answer» D. both lsi and vlsi | |
| 131. |
The D flip-flop has input. |
| A. | 1 |
| B. | 2 |
| C. | 3 |
| D. | 4 |
| Answer» A. 1 | |
| 132. |
The D flip-flop has output/outputs. |
| A. | 2 |
| B. | 3 |
| C. | 4 |
| D. | 1 |
| Answer» A. 2 | |
| 133. |
A D flip-flop can be constructed from an _ flip-flop. |
| A. | s-r |
| B. | j-k |
| C. | t |
| D. | s-k |
| Answer» A. s-r | |
| 134. |
In D flip-flop, if clock input is HIGH & D=1, then output is |
| A. | 0 |
| B. | 1 |
| C. | forbidden |
| D. | toggle |
| Answer» A. 0 | |
| 135. |
Which of the following is correct for a gated D flip-flop? |
| A. | the output toggles if one of the inputs is held high |
| B. | only one of the inputs can be high at a time |
| C. | the output complement follows the input when enabled |
| D. | q output follows the input d when the enable is high |
| Answer» D. q output follows the input d when the enable is high | |
| 136. |
With regard to a D latch |
| A. | the q output follows the d input when en is low |
| B. | the q output is opposite the d input when en is low |
| C. | the q output follows the d input when en is high |
| D. | the q output is high regardless of en’s input state |
| Answer» C. the q output follows the d input when en is high | |
| 137. |
Which of the following is correct for a D latch? |
| A. | the output toggles if one of the inputs is held high |
| B. | q output follows the input d when the enable is high |
| C. | only one of the inputs can be high at a time |
| D. | the output complement follows the input when enabled |
| Answer» B. q output follows the input d when the enable is high | |
| 138. |
Which of the following describes the operation of a positive edge-triggered D flip-flop? |
| A. | if both inputs are high, the output will toggle |
| B. | the output will follow the input on the leading edge of the clock |
| C. | when both inputs are low, an invalid state exists |
| D. | the input is toggled into the flip-flop on the leading edge of the clock and is passed to the output on the trailing edge of the clock |
| Answer» B. the output will follow the input on the leading edge of the clock | |
| 139. |
A positive edge-triggered D flip-flop will store a 1 when |
| A. | the d input is high and the clock transitions from high to low |
| B. | the d input is high and the clock transitions from low to high |
| C. | the d input is high and the clock is low |
| D. | the d input is high and the clock is high |
| Answer» B. the d input is high and the clock transitions from low to high | |
| 140. |
Why do the D flip-flops receive its designation or nomenclature as ‘Data Flip-flops’? |
| A. | due to its capability to receive data from flip-flop |
| B. | due to its capability to store data in flip-flop |
| C. | due to its capability to transfer the data into flip-flop |
| D. | due to erasing the data from the flip-flop |
| Answer» C. due to its capability to transfer the data into flip-flop | |
| 141. |
The characteristic equation of D-flip-flop implies that |
| A. | the next state is dependent on previous state |
| B. | the next state is dependent on present state |
| C. | the next state is independent of previous state |
| D. | the next state is independent of present state |
| Answer» D. the next state is independent of present state | |
| 142. |
The asynchronous input can be used to set the flip-flop to the |
| A. | 1 state |
| B. | 0 state |
| C. | either 1 or 0 state |
| D. | forbidden state |
| Answer» C. either 1 or 0 state | |
| 143. |
Input clock of RS flip-flop is given to |
| A. | input |
| B. | pulser |
| C. | output |
| D. | master slave flip-flop |
| Answer» B. pulser | |
| 144. |
D flip-flop is a circuit having |
| A. | 2 nand gates |
| B. | 3 nand gates |
| C. | 4 nand gates |
| D. | 5 nand gates |
| Answer» C. 4 nand gates | |
| 145. |
At the end of the clock pulse the value of output Q is uncertain. The situation is referred to as? |
| A. | conversion condition |
| B. | race around condition |
| C. | lock out state |
| D. | forbidden state |
| Answer» B. race around condition | |
| 146. |
Master slave flip flop is also referred to as? |
| A. | level triggered flip flop |
| B. | pulse triggered flip flop |
| C. | edge triggered flip flop |
| D. | edge-level triggered flip flop |
| Answer» B. pulse triggered flip flop | |
| 147. |
In a positive edge triggered JK flip flop, a low J and low K produces? |
| A. | high state |
| B. | low state |
| C. | toggle state |
| D. | no change state |
| Answer» D. no change state | |
| 148. |
If one wants to design a binary counter, the preferred type of flip-flop is |
| A. | d type |
| B. | s-r type |
| C. | latch |
| D. | j-k type |
| Answer» D. j-k type | |
| 149. |
S-R type flip-flop can be converted into D type flip-flop if S is connected to R through |
| A. | or gate |
| B. | and gate |
| C. | inverter |
| D. | full adder |
| Answer» C. inverter | |
| 150. |
Which of the following flip-flops is free from the race around the problem? |
| A. | t flip-flop |
| B. | sr flip-flop |
| C. | master-slave flip-flop |
| D. | d flip-flop |
| Answer» A. t flip-flop | |
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