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1. |
Any signed negative binary number is recognised by its |
A. | msb |
B. | lsb |
C. | byte |
D. | nibble |
Answer» A. msb |
2. |
The parameter through which 16 distinct values can be represented is known as |
A. | bit |
B. | byte |
C. | word |
D. | nibble |
Answer» C. word |
3. |
The representation of octal number (532.2)8 in decimal is |
A. | (346.25)10 |
B. | (532.864)10 |
C. | (340.67)10 |
D. | (531.668)10 |
Answer» A. (346.25)10 |
4. |
The decimal equivalent of the binary number (1011.011)2 is |
A. | (11.375)10 |
B. | (10.123)10 |
C. | (11.175)10 |
D. | (9.23)10 |
Answer» A. (11.375)10 |
5. |
An important drawback of binary system is |
A. | it requires very large string of 1’s and 0’s to represent a decimal number |
B. | it requires sparingly small string of 1’s and 0’s to represent a decimal number |
C. | it requires large string of 1’s and small string of 0’s to represent a decimal number |
D. | it requires small string of 1’s and large string of 0’s to represent a decimal number |
Answer» A. it requires very large string of 1’s and 0’s to represent a decimal number |
6. |
The decimal equivalent of the octal number (645)8 is |
A. | (450)10 |
B. | (451)10 |
C. | (421)10 |
D. | (501)10 |
Answer» C. (421)10 |
7. |
The largest two digit hexadecimal number is |
A. | (fe)16 |
B. | (fd)16 |
C. | (ff)16 |
D. | (ef)16 |
Answer» C. (ff)16 |
8. |
Representation of hexadecimal number (6DE)H in decimal: |
A. | 6 * 162 + 13 * 161 + 14 * 160 |
B. | 6 * 162 + 12 * 161 + 13 * 160 |
C. | 6 * 162 + 11 * 161 + 14 * 160 |
D. | 6 * 162 + 14 * 161 + 15 * 160 |
Answer» A. 6 * 162 + 13 * 161 + 14 * 160 |
9. |
The quantity of double word is |
A. | 16 bits |
B. | 32 bits |
C. | 4 bits |
D. | 8 bits |
Answer» B. 32 bits |
10. |
What does RTL in digital circuit design stand for? |
A. | register transfer language |
B. | register transfer logic |
C. | register transfer level |
D. | resistor-transistor logic |
Answer» C. register transfer level |
11. |
RTL is a design abstraction of what kind of circuit? |
A. | asynchronous digital circuit |
B. | synchronous digital circuit |
C. | asynchronous sequential circuit |
D. | analog circuit |
Answer» B. synchronous digital circuit |
12. |
RTL is used in HDL to create what level of representations in the circuit? |
A. | high-level |
B. | low-level |
C. | mid-level |
D. | same level |
Answer» A. high-level |
13. |
RTL mainly focuses on describing the flow of signals between |
A. | logic gates |
B. | registers |
C. | clock |
D. | inverter |
Answer» B. registers |
14. |
Which flip-flop is usually used in the implementation of the registers? |
A. | d flip-flop |
B. | s-r flip-flop |
C. | t flip-flop |
D. | j-k flip-flop |
Answer» A. d flip-flop |
15. |
Which of the following tool performs logic optimization? |
A. | simulation tool |
B. | synthesis tool |
C. | routing tool |
D. | rtl compiler |
Answer» B. synthesis tool |
16. |
Hold time is the time needed for the data to after the edge of the clock is triggered. |
A. | decrease |
B. | increase |
C. | remain constant |
D. | negate |
Answer» C. remain constant |
17. |
Simulator enters in which phase after the initialization phase? |
A. | execution phase |
B. | compilation phase |
C. | elaboration phase |
D. | simulation phase |
Answer» A. execution phase |
18. |
All input of NOR as low produces result as |
A. | low |
B. | mid |
C. | high |
D. | floating |
Answer» C. high |
19. |
In RTL NOR gate, the output is at logic 1 only when all the inputs are at |
A. | logic 0 |
B. | logic 1 |
C. | +10v |
D. | floating |
Answer» A. logic 0 |
20. |
The role of the is to convert the collector current into a voltage in RTL. |
A. | collector resistor |
B. | base resistor |
C. | capacitor |
D. | inductor |
Answer» A. collector resistor |
21. |
The limitations of the one transistor RTL NOR gate are overcome by |
A. | two-transistor rtl implementation |
B. | three-transistor rtl implementation |
C. | multi-transistor rtl implementation |
D. | four-transistor rtl implementation |
Answer» C. multi-transistor rtl implementation |
22. |
The primary advantage of RTL technology was that |
A. | it results as low power dissipation |
B. | it uses a minimum number of resistors |
C. | it uses a minimum number of transistors |
D. | it operates swiftly |
Answer» C. it uses a minimum number of transistors |
23. |
The disadvantage of RTL is that |
A. | it uses a maximum number of resistors |
B. | it results in high power dissipation |
C. | high noise creation |
D. | it uses minimum number of transistors |
Answer» B. it results in high power dissipation |
24. |
TTL circuits with “totem-pole” output stage minimize |
A. | the power dissipation in rtl |
B. | the time consumption in rtl |
C. | the speed of transferring rate in rtl |
D. | propagation delay in rtl |
Answer» A. the power dissipation in rtl |
25. |
The minimum number of transistors can be used by 2 input AND gate is |
A. | 2 |
B. | 3 |
C. | 4 |
D. | 5 |
Answer» A. 2 |
26. |
Diode–transistor logic (DTL) is the direct ancestor of |
A. | register-transistor logic |
B. | transistor–transistor logic |
C. | high threshold logic |
D. | emitter coupled logic |
Answer» B. transistor–transistor logic |
27. |
In DTL logic gating function is performed by |
A. | diode |
B. | transistor |
C. | inductor |
D. | capacitor |
Answer» A. diode |
28. |
In DTL amplifying function is performed by |
A. | diode |
B. | transistor |
C. | inductor |
D. | capacitor |
Answer» B. transistor |
29. |
How many stages a DTL consist of? |
A. | 2 |
B. | 3 |
C. | 4 |
D. | 5 |
Answer» B. 3 |
30. |
The full form of CTDL is |
A. | complemented transistor diode logic |
B. | complemented transistor direct logic |
C. | complementary transistor diode logic |
D. | complementary transistor direct logic |
Answer» A. complemented transistor diode logic |
31. |
The DTL propagation delay is relatively |
A. | large |
B. | small |
C. | moderate |
D. | negligible |
Answer» A. large |
32. |
The way to speed up DTL is to add an across intermediate resister is |
A. | small “speed-up” capacitor |
B. | large “speed-up” capacitor |
C. | small “speed-up” transistor |
D. | large ” speed-up” transistor |
Answer» A. small “speed-up” capacitor |
33. |
The process to avoid saturating the switching transistor is performed by |
A. | baker clamp |
B. | james r. biard |
C. | chris brown |
D. | totem-pole |
Answer» A. baker clamp |
34. |
A major advantage of DTL over the earlier resistor–transistor logic is the |
A. | increased fan out |
B. | increased fan in |
C. | decreased fan out |
D. | decreased fan in |
Answer» B. increased fan in |
35. |
To increase fan-out of the gate in DTL |
A. | an additional capacitor may be used |
B. | an additional resister may be used |
C. | an additional transistor and diode may be used |
D. | only an additional diode may be used |
Answer» C. an additional transistor and diode may be used |
36. |
A disadvantage of DTL is |
A. | the input transistor to the resister |
B. | the input resister to the transistor |
C. | the increased fan-in |
D. | the increased fan-out |
Answer» B. the input resister to the transistor |
37. |
Compatibility refers to |
A. | the output of a circuit should match with the input of another circuit |
B. | the output of a circuit should match with the input of the same circuit |
C. | the input of a circuit should match with the output of another circuit |
D. | the input of a circuit should match with the output of same circuit |
Answer» A. the output of a circuit should match with the input of another circuit |
38. |
The method of connecting a driving device to a loading device is known as |
A. | compatibility |
B. | interface |
C. | sourcing |
D. | sinking |
Answer» B. interface |
39. |
The first CML logic was introduced by General Electric in |
A. | 1960 |
B. | 1981 |
C. | 1961 |
D. | 1990 |
Answer» C. 1961 |
40. |
Schottky families prevent the saturating using |
A. | transistors |
B. | schottky transistors |
C. | diodes |
D. | schottky diodes |
Answer» D. schottky diodes |
41. |
The basic idea of basic CML circuit came from an |
A. | inverter |
B. | buffer |
C. | transistor |
D. | both inverter and buffer |
Answer» D. both inverter and buffer |
42. |
The full form of MECL is |
A. | mono emitter coupled logic |
B. | motorola emitter coupled logic |
C. | motorola emitter capacitor logic |
D. | both mono emitter and motorola coupled logic |
Answer» B. motorola emitter coupled logic |
43. |
Motorola has offered MECL circuits in logic families. |
A. | 3 |
B. | 4 |
C. | 5 |
D. | 6 |
Answer» C. 5 |
44. |
The latest entrant to the ECL family is |
A. | ecl 10k |
B. | ecl 100k |
C. | ecl 1000k |
D. | ecl 10000k |
Answer» B. ecl 100k |
45. |
All input of NOR as low produces result as |
A. | low |
B. | mid |
C. | high |
D. | high impedance |
Answer» C. high |
46. |
In RTL NOR gate, the output is at logic 1 only when all the inputs are at |
A. | logic 0 |
B. | logic 1 |
C. | +10v |
D. | floating |
Answer» A. logic 0 |
47. |
The full form of CMOS is |
A. | capacitive metal oxide semiconductor |
B. | capacitive metallic oxide semiconductor |
C. | complementary metal oxide semiconductor |
D. | complemented metal oxide semiconductor |
Answer» C. complementary metal oxide semiconductor |
48. |
The full form of COS-MOS is |
A. | complementary symmetry metal oxide semiconductor |
B. | complementary systematic metal oxide semiconductor |
C. | capacitive symmetry metal oxide semiconductor |
D. | complemented systematic metal oxide semiconductor |
Answer» A. complementary symmetry metal oxide semiconductor |
49. |
CMOS is also sometimes referred to as |
A. | capacitive metal oxide semiconductor |
B. | capacitive symmetry metal oxide semiconductor |
C. | complementary symmetry metal oxide semiconductor |
D. | complemented symmetry metal oxide semiconductor |
Answer» C. complementary symmetry metal oxide semiconductor |
50. |
CMOS technology is used in |
A. | inverter |
B. | microprocessor |
C. | digital logic |
D. | both microprocessor and digital logic |
Answer» D. both microprocessor and digital logic |
51. |
Two important characteristics of CMOS devices are |
A. | high noise immunity |
B. | low static power consumption |
C. | high resistivity |
D. | both high noise immunity and low static power consumption |
Answer» D. both high noise immunity and low static power consumption |
52. |
CMOS behaves as a/an |
A. | adder |
B. | subtractor |
C. | inverter |
D. | comparator |
Answer» C. inverter |
53. |
An important characteristic of a CMOS circuit is the |
A. | noise immunity |
B. | duality |
C. | symmetricity |
D. | noise margin |
Answer» B. duality |
54. |
CMOS logic dissipates power than NMOS logic circuits. |
A. | more |
B. | less |
C. | equal |
D. | very high |
Answer» B. less |
55. |
Semiconductors are made of |
A. | ge and si |
B. | si and pb |
C. | ge and pb |
D. | pb and au |
Answer» A. ge and si |
56. |
Which chip were the first RTC and CMOS RAM chip to be used in early IBM computers, capable of storing a total of 64 bytes? |
A. | the samsung 146818 |
B. | the samsung 146819 |
C. | the motorola 146818 |
D. | the motorola 146819 |
Answer» C. the motorola 146818 |
57. |
The full form of ECL is |
A. | emitter-collector logic |
B. | emitter-complementary logic |
C. | emitter-coupled logic |
D. | emitter-cored logic |
Answer» C. emitter-coupled logic |
58. |
Which logic is the fastest of all the logic families? |
A. | ttl |
B. | ecl |
C. | htl |
D. | dtl |
Answer» B. ecl |
59. |
Sometimes ECL can also be named as |
A. | eel |
B. | cel |
C. | cml |
D. | ccl |
Answer» C. cml |
60. |
In an ECL the output is taken from |
A. | emitter |
B. | base |
C. | collector |
D. | junction of emitter and base |
Answer» C. collector |
61. |
The ECL behaves as |
A. | not gate |
B. | nor gate |
C. | nand gate |
D. | and gate |
Answer» B. nor gate |
62. |
In ECL the fanout capability is |
A. | high |
B. | low |
C. | zero |
D. | sometimes high and sometimes low |
Answer» A. high |
63. |
ECL’s major disadvantage is that |
A. | it requires more power |
B. | it’s fanout capability is high |
C. | it creates more noise |
D. | it is slow |
Answer» A. it requires more power |
64. |
The full form of SCFL is |
A. | source-collector logic |
B. | source-coupled logic |
C. | source-complementary logic |
D. | source cored logic |
Answer» B. source-coupled logic |
65. |
The equivalent of emitter-coupled logic made out of FETs is called |
A. | cml |
B. | scfl |
C. | fecl |
D. | efcl |
Answer» B. scfl |
66. |
ECL was invented in by |
A. | 1956, baker clamp |
B. | 1976, james r. biard |
C. | 1956, hannon s. yourke |
D. | 1976, yourke |
Answer» C. 1956, hannon s. yourke |
67. |
At the time of invention, an ECL was called as |
A. | source-coupled logic |
B. | current mode logic |
C. | current-steering logic |
D. | emitter-coupled logic |
Answer» C. current-steering logic |
68. |
The ECL circuits usually operates with |
A. | negative voltage |
B. | positive voltage |
C. | grounded voltage |
D. | high voltage |
Answer» A. negative voltage |
69. |
Low-voltage positive emitter-coupled logic (LVPECL) is a power optimized version of |
A. | ecl |
B. | vecl |
C. | pecl |
D. | lecl |
Answer» C. pecl |
70. |
Transistor–transistor logic (TTL) is a class of digital circuits built from |
A. | jfet only |
B. | bipolar junction transistors (bjt) |
C. | resistors |
D. | bipolar junction transistors (bjt) and resistors |
Answer» D. bipolar junction transistors (bjt) and resistors |
71. |
TTL was invented in 1961 by |
A. | baker clamp |
B. | james l. buie |
C. | chris brown |
D. | frank wanlass |
Answer» B. james l. buie |
72. |
The full form of TCTL is |
A. | transistor-coupled transistor logic |
B. | transistor-capacitor transistor logic |
C. | transistor-complemented transistor logic |
D. | transistor-complementary transistor logic |
Answer» A. transistor-coupled transistor logic |
73. |
The ancestor to the first personal computers. |
A. | param 1 |
B. | satyam 1 |
C. | kenbak 1 |
D. | mits altair |
Answer» C. kenbak 1 |
74. |
TTL inputs are the emitters of a |
A. | transistor-transistor logic |
B. | multiple-emitter transistor |
C. | resistor-transistor logic |
D. | diode-transistor logic |
Answer» B. multiple-emitter transistor |
75. |
TTL is a |
A. | current sinking |
B. | current sourcing |
C. | voltage sinking |
D. | voltage sourcing |
Answer» A. current sinking |
76. |
Standard TTL circuits operate with a volt power supply. |
A. | 2 |
B. | 4 |
C. | 5 |
D. | 3 |
Answer» C. 5 |
77. |
A TTL gate may operate inadvertently as an |
A. | digital amplifier |
B. | analog amplifier |
C. | inverter |
D. | regulator |
Answer» B. analog amplifier |
78. |
Which statement below best describes a Karnaugh map? |
A. | it is simply a rearranged truth table |
B. | the karnaugh map eliminates the need for using nand and nor gates |
C. | variable complements can be eliminated by using karnaugh maps |
D. | a karnaugh map can be used to replace boolean rules |
Answer» A. it is simply a rearranged truth table |
79. |
Which of the examples below expresses the commutative law of multiplication? |
A. | a + b = b + a |
B. | a • b = b + a |
C. | a • (b • c) = (a • b) • c |
D. | a • b = b • a |
Answer» D. a • b = b • a |
80. |
The Boolean expression Y = (AB)’ is logically equivalent to what single gate? |
A. | nand |
B. | nor |
C. | and |
D. | or |
Answer» A. nand |
81. |
The systematic reduction of logic circuits is accomplished by: |
A. | symbolic reduction |
B. | ttl logic |
C. | using boolean algebra |
D. | using a truth table |
Answer» C. using boolean algebra |
82. |
Each “1” entry in a K-map square represents: |
A. | a high for each input truth table condition that produces a high output |
B. | a high output on the truth table for all low input combinations |
C. | a low output for all possible high input conditions |
D. | a don’t care condition for all possible input truth table combinations |
Answer» A. a high for each input truth table condition that produces a high output |
83. |
Each “0” entry in a K-map square represents: |
A. | a high for each input truth table condition that produces a high output |
B. | a high output on the truth table for all low input combinations |
C. | a low output for all possible high input conditions |
D. | a don’t care condition for all possible input truth table combinations |
Answer» A. a high for each input truth table condition that produces a high output |
84. |
Looping on a K-map always results in the elimination of |
A. | variables within the loop that appear only in their complemented form |
B. | variables that remain unchanged within the loop |
C. | variables within the loop that appear in both complemented and uncomplemented form |
D. | variables within the loop that appear only in their uncomplemented form |
Answer» C. variables within the loop that appear in both complemented and uncomplemented form |
85. |
Which of the following expressions is in the sum-of-products form? |
A. | (a + b)(c + d) |
B. | (a * b)(c * d) |
C. | a* b *(cd) |
D. | a * b + c * d |
Answer» D. a * b + c * d |
86. |
What is an ambiguous condition in a NAND based S’-R’ latch? |
A. | s’=0, r’=1 |
B. | s’=1, r’=0 |
C. | s’=1, r’=1 |
D. | s’=0, r’=0 |
Answer» D. s’=0, r’=0 |
87. |
In a NAND based S’-R’ latch, if S’=1 & R’=1 then the state of the latch is |
A. | no change |
B. | set |
C. | reset |
D. | forbidden |
Answer» A. no change |
88. |
A NAND based S’-R’ latch can be converted into S-R latch by placing |
A. | a d latch at each of its input |
B. | an inverter at each of its input |
C. | it can never be converted |
D. | both a d latch and an inverter at its input |
Answer» D. both a d latch and an inverter at its input |
89. |
The difference between a flip-flop & latch is |
A. | both are same |
B. | flip-flop consist of an extra output |
C. | latches has one input but flip-flop has two |
D. | latch has two inputs but flip-flop has one |
Answer» C. latches has one input but flip-flop has two |
90. |
How many types of flip-flops are? |
A. | 2 |
B. | 3 |
C. | 4 |
D. | 5 |
Answer» C. 4 |
91. |
The S-R flip flop consist of |
A. | 4 and gates |
B. | two additional and gates |
C. | an additional clock input |
D. | 3 and gates |
Answer» B. two additional and gates |
92. |
What is one disadvantage of an S-R flip-flop? |
A. | it has no enable input |
B. | it has a race condition |
C. | it has no clock input |
D. | invalid state |
Answer» D. invalid state |
93. |
One example of the use of an S-R flip-flop is as |
A. | racer |
B. | stable oscillator |
C. | binary storage register |
D. | transition pulse generator |
Answer» C. binary storage register |
94. |
When is a flip-flop said to be transparent? |
A. | when the q output is opposite the input |
B. | when the q output follows the input |
C. | when you can see through the ic packaging |
D. | when the q output is complementary of the input |
Answer» B. when the q output follows the input |
95. |
On a positive edge-triggered S-R flip-flop, the outputs reflect the input condition when |
A. | the clock pulse is low |
B. | the clock pulse is high |
C. | the clock pulse transitions from low to high |
D. | the clock pulse transitions from high to low |
Answer» C. the clock pulse transitions from low to high |
96. |
What is the hold condition of a flip-flop? |
A. | both s and r inputs activated |
B. | no active s or r input |
C. | only s is active |
D. | only r is active |
Answer» B. no active s or r input |
97. |
One example of the use of an S-R flip-flop is as |
A. | transition pulse generator |
B. | racer |
C. | switch debouncer |
D. | astable oscillator |
Answer» C. switch debouncer |
98. |
The truth table for an S-R flip-flop has how many VALID entries? |
A. | 1 |
B. | 2 |
C. | 3 |
D. | 4 |
Answer» C. 3 |
99. |
When both inputs of a J-K flip-flop cycle, the output will |
A. | be invalid |
B. | change |
C. | not change |
D. | toggle |
Answer» C. not change |
100. |
Which of the following is correct for a gated D-type flip-flop? |
A. | the q output is either set or reset as soon as the d input goes high or low |
B. | the output complement follows the input when enabled |
C. | only one of the inputs can be high at a time |
D. | the output toggles if one of the inputs is held high |
Answer» A. the q output is either set or reset as soon as the d input goes high or low |
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