McqMate
These multiple-choice questions (MCQs) are designed to enhance your knowledge and understanding in the following areas: Electrical Engineering .
| 51. |
Consider the circuit shown. VDS=3 V. If IDS=2mA, find VDD to bias circuit. |
| A. | -30v |
| B. | 30v |
| C. | 33v |
| D. | any value of voltage less than 12 v |
| Answer» C. 33v | |
| Explanation: vds = vdd – ids(10k + 5k) 3 = vdd – 2(15) | |
| 52. |
To bias a e-MOSFET |
| A. | we can use either gate bias or a voltage divider bias circuit |
| B. | we can use either gate bias or a self bias circuit |
| C. | we can use either self bias or a voltage divider bias circuit |
| D. | we can use any type of bias circuit |
| Answer» A. we can use either gate bias or a voltage divider bias circuit | |
| Explanation: to bias an e-mosfet, we cannot use a self bias circuit because the gate to source voltage for such a circuit is zero. | |
| 53. |
Consider the following circuit. IDSS = 2mA, VDD = 30V. Find R, given that VP = – 2V. |
| A. | 10kΩ |
| B. | 4kΩ |
| C. | 2kΩ |
| D. | 5kΩ |
| Answer» B. 4kΩ | |
| Explanation: idss = 2ma | |
| 54. |
Process transconductance parameter is 40μA/V2. Find drain to source current in saturation. |
| A. | 0.10 ma |
| B. | 0.05ma |
| C. | – 0.05ma |
| D. | – 50a |
| Answer» C. – 0.05ma | |
| Explanation: isd = k’w(vsg – | |
| 55. |
Consider the following circuit. Given that VDD = 15V, VP = 2V, and IDS = 3mA, to bias the circuit properly, select the proper statement. |
| A. | rd < 6kΩ |
| B. | rd > 6kΩ |
| C. | rd > 4kΩ |
| D. | rd < 4kΩ |
| Answer» A. rd < 6kΩ | |
| Explanation: in given circuit, vgs = -5v vds = vdd – idsrd | |
| 56. |
Consider the following circuit. Process transconductance parameter = 0.50 mA/V2, W/L=1, Threshold voltage = 3V, VDD = 20V. Find the operating point of circuit. |
| A. | 20v, 25ma |
| B. | 13v, 22ma |
| C. | 12.72v, 23.61ma |
| D. | 20v, 23.61ma |
| Answer» C. 12.72v, 23.61ma | |
| Explanation: ids = [k’w/l(vgs – vt)2]/2 vgs = 20 x 35 / 55 = 12.72 v | |
| 57. |
Which of the following relation is true about gate current? |
| A. | ig=id+is |
| B. | id=ig |
| C. | is= ig |
| D. | ig=0 |
| Answer» D. ig=0 | |
| Explanation: the fet physical structure which contains silicon dioxide provides infinite resistance. hence no current will flow through the gate terminal. | |
| 58. |
For a fixed bias circuit the drain current was 1mA, what is the value of source current? |
| A. | 0ma |
| B. | 1ma |
| C. | 2ma |
| D. | 3ma |
| Answer» C. 2ma | |
| Explanation: we know that for an fet same current flows through the gate and source terminal, hence source current=1ma. | |
| 59. |
For a fixed bias circuit the drain current was 1mA, VDD=12V, determine drain resistance required if VDS=10V? |
| A. | 1kΩ |
| B. | 1.5kΩ |
| C. | 2kΩ |
| D. | 4kΩ |
| Answer» C. 2kΩ | |
| Explanation: vds=vdd-id rd | |
| 60. |
Which of the following equation brings the relation between gate to source voltage and drain current in Self Bias? |
| A. | vgs=vdd |
| B. | vgs=-id rs |
| C. | vgs=0 |
| D. | vgs=1+id rs |
| Answer» B. vgs=-id rs | |
| Explanation: vrs=id rs | |
| 61. |
For a self-bias circuit, find drain to source voltage if VDD=12V, ID=1mA, Rs=RD=1KΩ? |
| A. | 1v |
| B. | 2v |
| C. | 10v |
| D. | 5v |
| Answer» C. 10v | |
| Explanation: vds=vdd-id (rd+rs) | |
| 62. |
Find the gate voltage for voltage divider having R1=R2=1KΩ and VDD=5V? |
| A. | 1v |
| B. | 5v |
| C. | 3v |
| D. | 2.5v |
| Answer» D. 2.5v | |
| Explanation: vg = r2×vdd/r1+r2 | |
| 63. |
Find the gate to source voltage for voltage divider having R1=R2=2KΩ and VDD=12V, ID=1mA and RS=4KΩ? |
| A. | 3v |
| B. | 2v |
| C. | 0v |
| D. | 1v |
| Answer» B. 2v | |
| Explanation: vg = r2×vdd/r1+r2 | |
| 64. |
What will happen if values of Rs increase? |
| A. | vgs increases |
| B. | vgs decreases |
| C. | vgs remains the same |
| D. | vgs=0 |
| Answer» B. vgs decreases | |
| Explanation: increasing values of rs result in lower quiescent values of id and more negative values of vgs. | |
| 65. |
What is the current flowing through the R1 resistor for voltage divider (R1=R2=1KΩ, VDD=10V)? |
| A. | 5ma |
| B. | 3ma |
| C. | 1ma |
| D. | 2ma |
| Answer» A. 5ma | |
| Explanation: ir1=ir2 =vdd/r1+r2 | |
| 66. |
The h-parameters analysis gives correct results for |
| A. | large signals only |
| B. | small signals only |
| C. | both large and small |
| D. | not large nor small signals |
| Answer» B. small signals only | |
| Explanation: every linear circuit is associated with h –parameters. when this linear circuit is terminated with load rl, we can find input impedance, current gain, voltage gain, etc in terms of h-parameters. | |
| 67. |
For what type of signals does a transistor behaves as linear device? |
| A. | small signals only |
| B. | large signals only |
| C. | both large and small signal |
| D. | no signal |
| Answer» A. small signals only | |
| Explanation: the small variation in the total voltage and current due to an application of signal moves the point up and down just by a bit and that whole up and down dynamics of the operating point from its dc value point can be approximated to be along a straight line. whole analysis can be done with same assumption of linearity with the limit of signal being in the same vicinity of the dc operating point. | |
| 68. |
How many h-parameters are there for a transistor? |
| A. | two |
| B. | three |
| C. | four |
| D. | five |
| Answer» C. four | |
| Explanation: a transistor has four h- parameters – | |
| 69. |
The dimensions of hie parameters are |
| A. | mho |
| B. | ohm |
| C. | farad |
| D. | ampere |
| Answer» B. ohm | |
| Explanation: hie = vbe/ib; common emitter input impedance | |
| 70. |
The hfe parameter is called in CE arrangement with output short circuited. |
| A. | voltage gain |
| B. | current gain |
| C. | input impedance |
| D. | output impedance |
| Answer» B. current gain | |
| Explanation: hfe in ce arrangement is given as | |
| 71. |
What happens to the h parameters of a transistor when the operating point of the transistor changes? |
| A. | it also changes |
| B. | does not change |
| C. | may or may not change |
| D. | nothing happens |
| Answer» A. it also changes | |
| Explanation: it is very difficult to get exact values of h parameters for a particular transistor. it is because these parameters are subject to considerable variation unit to unit variation, variation due to change in temperature and variation due to the operating point. | |
| 72. |
If temperature changes, h parameters of a transistor |
| A. | also change |
| B. | does not change |
| C. | remains same |
| D. | may or may not change |
| Answer» A. also change | |
| Explanation: it is very difficult to get exact values of h parameters for a particular transistor. it is because these parameters are subject to considerable variation unit to unit variation, variation due to change in temperature and variation due to the operating point. | |
| 73. |
In CE arrangement, the value of input impedance is approximately equal to |
| A. | hie |
| B. | hib |
| C. | hoe |
| D. | hre |
| Answer» A. hie | |
| Explanation: hie = vbe/ib; common emitter input impedance | |
| 74. |
How many h-parameters of a transistor are dimensionless? |
| A. | four |
| B. | two |
| C. | three |
| D. | one |
| Answer» B. two | |
| Explanation: (i) h11 = v1/i1; for v2 = 0 (output short circuited) | |
| 75. |
The values of h-parameters of a transistor in CE arrangement are arrangement. |
| A. | same as for cb |
| B. | same as for cc |
| C. | different from that in cb |
| D. | similar to no |
| Answer» C. different from that in cb | |
| Explanation: the values of h-parameter in ce arrangement: | |
| 76. |
If the load resistance of a C.E. stage increases by a factor of 2, what happens to the high frequency response? |
| A. | the 3 db roll off occurs faster |
| B. | the 3 db roll off occurs later |
| C. | the input pole shifts towards origin |
| D. | the input pole becomes infinite |
| Answer» A. the 3 db roll off occurs faster | |
| Explanation: if the load resistance increases by a factor of 2, the output pole decreases since it’s inversely proportional to the load resistance. hence the c.e. stage experiences a faster roll off due to the pole. | |
| 77. |
During high frequency applications of a B.J.T., which of the following three stages do not get affected by Miller’s approximation? |
| A. | c.e. |
| B. | c.b. |
| C. | c.c. |
| D. | follower |
| Answer» B. c.b. | |
| Explanation: during the c.b. stage, the capacitance between the base and the collector doesn’t suffer from miller approximation since the input is applied to the emitter of the b.j.t. there are no capacitors connected between two nodes having a constant gain. hence the c.b. stage doesn’t get affected by miller approximation. | |
| 78. |
Ignoring early effect, if C1 is the total capacitance tied to the emitter, what is the input pole of a simple C.B. stage? |
| A. | 1/gm * c1 |
| B. | 2/gm * c1 |
| C. | gm * c1 |
| D. | gm * 2c1 |
| Answer» A. 1/gm * c1 | |
| Explanation: the resistance looking into the | |
| 79. |
In a simple follower stage, C2 is a parasitic capacitance arising due to the depletion region between the collector and the substrate. What is the value of C2? |
| A. | 0 |
| B. | infinite |
| C. | ccs |
| D. | 2*ccs |
| Answer» A. 0 | |
| Explanation: during the high frequency response, the capacitor between the collector and the substrate gets shorted to a.c. ground at both of its terminals. hence, c2=0. the answer would have been ccs for any other stage of b.j.t. | |
| 80. |
For a cascode stage, with input applied to the C.B. stage, the input capacitance gets multiplied by a factor of |
| A. | 0 |
| B. | 1 |
| C. | 3 |
| D. | 2 |
| Answer» D. 2 | |
| Explanation: the small signal gain, of the | |
| 81. |
If the B.J.T. is used as a follower, which capacitor experiences Miller multiplication? |
| A. | cπ |
| B. | cµ |
| C. | ccs |
| D. | cb |
| Answer» A. cπ | |
| Explanation: we find that the input is given to the base of the b.j.t. while the output is | |
| 82. |
If 1/h12 = 4, for a C.E. stage- what is the value of the base to collector capacitance, after Miller multiplication, at the input side? |
| A. | 4cµ |
| B. | 5cµ |
| C. | 6cµ |
| D. | 1.1cµ |
| Answer» C. 6cµ | |
| Explanation: the capacitor, cµ, gets multiplied by a factor of (1 + av), at the input side of a c.e. stage. 1/h12 is equal to av since h12 is the reverse voltage amplification factor. hence, the final value becomes 5cµ. | |
| 83. |
The transconductance of a B.J.T.is 5mS (gm) while a 2KΩ (Rl) load resistance is connected to the C.E. stage. Neglecting Early effect, what is the Miller multiplication factor for the input side? |
| A. | 21 |
| B. | 11 |
| C. | 20 |
| D. | 0 |
| Answer» B. 11 | |
| Explanation: the miller multiplication factor for the input side of a c.e. stage is (1+av). | |
| 84. |
Which of these are incorrect about Darlington amplifier? |
| A. | it has a high input resistance |
| B. | the output resistance is low |
| C. | it has a unity voltage gain |
| D. | it is a current buffer |
| Answer» D. it is a current buffer | |
| Explanation: a darlington amplifier has a very high input resistance, low output resistance, unity voltage gain and a high current gain. it is a voltage buffer, not a current buffer. | |
| 85. |
In a Darlington pair, the overall β=15000.β1=100. Calculate the collector current for Q2 given base current for Q1 is 20 μA. |
| A. | 300 ma |
| B. | 298 ma |
| C. | 2 ma |
| D. | 200ma |
| Answer» B. 298 ma | |
| Explanation: ib = 20 μa | |
| 86. |
What is the need for bootstrap biasing? |
| A. | to prevent a decrease in the gain of network |
| B. | to prevent an increase in the input resistance due to the biasing network |
| C. | to prevent a decrease in the input resistance due to the presence of multiple bjt amplifiers |
| D. | to prevent a decrease in the input resistance due to the biasing network |
| Answer» B. to prevent an increase in the input resistance due to the biasing network | |
| Explanation: a bootstrap biasing network is a special biasing circuit used in darlington amplifier to prevent the decrease in input resistance due to the biasing network being used. capacitors and resistors are added to the circuit to prevent it from happening. | |
| 87. |
Consider a Darlington amplifier. In the self bias network, the biasing resistances are 220kΩ and 400 kΩ. What can be the correct value of input resistance if hfe=50 and emitter resistance = 10kΩ. |
| A. | 141 kΩ |
| B. | 15 mΩ |
| C. | 20 mΩ |
| D. | 200 kΩ |
| Answer» A. 141 kΩ | |
| Explanation: r’ = 220k | |
| 88. |
What is a cascode amplifier? |
| A. | a cascade of two ce amplifiers |
| B. | a cascade of two cb amplifiers |
| C. | a cascade of ce and cb amplifiers |
| D. | a cascade of cb and cc amplifiers |
| Answer» C. a cascade of ce and cb amplifiers | |
| Explanation: a cascode amplifier is a cascade network of ce and cb amplifiers, or cs and cg amplifiers. | |
| 89. |
1, α2 = 1.5 what is the transconductance of the entire network? |
| A. | 80 mΩ-1 |
| B. | 75 mΩ-1 |
| C. | 33 mΩ-1 |
| D. | 55 mΩ-1 |
| Answer» D. 55 mΩ-1 | |
| Explanation: the above circuit is a cascode pair. for this circuit, the overall transconductance is | |
| 90. |
In the given circuit, hfe = 50 and hie = 1000Ω, find overall input and output resistance. |
| A. | ri=956Ω, ro=1.6 kΩ |
| B. | ri=956 kΩ, ro=2 kΩ |
| C. | ri=956 Ω, ro=2 kΩ |
| D. | ri=900Ω, ro=10 kΩ |
| Answer» C. ri=956 Ω, ro=2 kΩ | |
| Explanation: ro = rc = 2kΩ | |
| 91. |
A Differential Amplifier should have collector resistor’s value (RC1 & RC2) as |
| A. | 5kΩ, 5kΩ |
| B. | 5Ω, 10kΩ |
| C. | 5Ω, 5kΩ |
| D. | 5kΩ, 10kΩ |
| Answer» A. 5kΩ, 5kΩ | |
| Explanation: the values of collector current will be equal in differential amplifier (rc1=rc2). | |
| 92. |
A Differential Amplifier amplifies |
| A. | input signal with higher voltage |
| B. | input voltage with smaller voltage |
| C. | sum of the input voltage |
| D. | none of the mentioned |
| Answer» D. none of the mentioned | |
| Explanation: the purpose of differential amplifier is to amplify the difference between two signals. | |
| 93. |
If output is measured between two collectors of transistors, then the Differential amplifier with two input signal is said to be configured as |
| A. | dual input balanced output |
| B. | dual input unbalanced output |
| C. | single input balanced output |
| D. | dual input unbalanced output |
| Answer» A. dual input balanced output | |
| Explanation: when two input signals are applied to base of transistor, it is said to be dual input. when both collectors are at same dc potential with respect to ground, then it is said to be balance output. | |
| 94. |
A differential amplifier is capable of amplifying |
| A. | dc input signal only |
| B. | ac input signal only |
| C. | ac & dc input signal |
| D. | none of the mentioned |
| Answer» C. ac & dc input signal | |
| Explanation: direct connection between stages removes the lower cut off frequency imposed by coupling capacitor; therefore it can amplify both ac and dc signal. | |
| 95. |
In ideal Differential Amplifier, if same signal is given to both inputs, then output will be |
| A. | same as input |
| B. | double the input |
| C. | not equal to zero |
| D. | zero |
| Answer» D. zero | |
| Explanation: in ideal amplifier, output voltage | |
| 96. |
Find IC, given VCE=0.77v, VCC=10v, VBE=0.37v and RC=2.4kΩ in Dual Input Balanced Output differential amplifier |
| A. | 0.4ma |
| B. | 0.4a |
| C. | 4ma |
| D. | b) d) 4a |
| Answer» C. 4ma | |
| Explanation: substitute the values in collector to emitter voltage equation, vce= vcc+ vbe-rc ic | |
| 97. |
Obtain the collector voltage, for collector resistor (RC) =5.6kΩ, IE=1.664mA and VCC=10v for single input unbalanced output differential amplifier |
| A. | 0.987v |
| B. | 0.682v |
| C. | 0.555v |
| D. | none of the mentioned |
| Answer» B. 0.682v | |
| Explanation: substitute the given values in collector voltage equation, | |
| 98. |
In a Single Input Balanced Output Differential amplifier, given VCC=15v, RE = 3.9kΩ, VCE=2.4 v and re=250Ω. Determine Voltage gain |
| A. | 26 |
| B. | 56 |
| C. | 38 |
| D. | 61 |
| Answer» A. 26 | |
| 99. |
For the difference amplifier which of the following is true? |
| A. | it responds to the difference between the two signals and rejects the signal that are common to both the signal |
| B. | it responds to the signal that are common to the two inputs only |
| C. | it has a low value of input resistance |
| D. | the efficacy of the amplifier is measured by the degree of its differential signal to the preference of the common mode signal |
| Answer» A. it responds to the difference between the two signals and rejects the signal that are common to both the signal | |
| Explanation: all the statements are not true except for the fact that it responds only when there is difference between two signals only. | |
| 100. |
The problem with the single operational difference amplifier is its |
| A. | high input resistance |
| B. | low input resistance |
| C. | low output resistance |
| D. | none of the mentioned |
| Answer» B. low input resistance | |
| Explanation: due to low input resistance a large part of the signal is lost to the source’s internal resistance. | |
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