McqMate
These multiple-choice questions (MCQs) are designed to enhance your knowledge and understanding in the following areas: Computer Science Engineering (CSE) , Electronics and Telecommunication Engineering [ENTC] .
| 501. |
Which of the following flip-flop is free from race-around problem ? |
| A. | q flip-flop |
| B. | t flip-flop |
| C. | sr flip-flop |
| D. | master- slave jk flip-flop |
| Answer» D. master- slave jk flip-flop | |
| 502. |
If the input J is connected through K input of J-K, then flip-flop will behave as a |
| A. | d type flip-flop |
| B. | t type flip- flop |
| C. | s-r flip-flop |
| D. | master slave jk flip-flop |
| Answer» A. d type flip-flop | |
| 503. |
If a clock with time period 'T' is used with n stage shift register, then output of final stage will be delayed by |
| A. | nt sec |
| B. | (n-1)t sec |
| C. | n/t sec |
| D. | (2n+1)t sec |
| Answer» B. (n-1)t sec | |
| 504. |
Register is a |
| A. | set of capacitor used to register input instructions in a digital computer |
| B. | set to paper tapes and cards put in a file |
| C. | temporary storage unit within the cpu having dedicated or general purpose use |
| D. | part of the main memory |
| Answer» C. temporary storage unit within the cpu having dedicated or general purpose use | |
| 505. |
The number of flip-flops required in a decade counter is |
| A. | 3 |
| B. | 4 |
| C. | 8 |
| D. | 10 |
| Answer» B. 4 | |
| 506. |
If in a shift resistor Q0 is fed back to input the resulting counter is |
| A. | twisted ring with n : 1 scale |
| B. | ring counter with n : 1 scale |
| C. | twisted ring with 2n : 1 scale |
| D. | ring counter with 2 n : 1 scale |
| Answer» C. twisted ring with 2n : 1 scale | |
| 507. |
A 8-bit serial in / parallel out shift register contains the value “8”, clock signal(s) will be required to shift the value completely out of the register. |
| A. | 1 |
| B. | 2 |
| C. | 4 |
| D. | 8 |
| Answer» D. 8 | |
| 508. |
In a sequential circuit the next state is determined by and |
| A. | state variable, current state |
| B. | current state, flip- flop output |
| C. | current state and external input |
| D. | input and clock signal applied |
| Answer» D. input and clock signal applied | |
| 509. |
The divide-by-60 counter in digital clock is implemented by using two cascading counters: |
| A. | mod-6, mod-10 |
| B. | mod-50, mod-10 |
| C. | mod-10, mod-50 |
| D. | mod-50, mod-6 |
| Answer» A. mod-6, mod-10 | |
| 510. |
In NOR gate based S-R latch if both S and R inputs are set to logic 0, the previous output state is maintained. |
| A. | true |
| B. | false |
| Answer» A. true | |
| 511. |
The minimum time for which the input signal has to be maintained at the input of flip-flop is called of the flip-flop. |
| A. | set-up time |
| B. | hold time |
| C. | pulse interval time |
| D. | pulse stability time (pst) |
| Answer» B. hold time | |
| 512. |
74HC163 has two enable input pins which are and |
| A. | enp, ent |
| B. | eni, enc |
| C. | enp, enc |
| D. | ent, eni |
| Answer» A. enp, ent | |
| 513. |
to change in one input variable |
| A. | clock skew |
| B. | condition |
| C. | hold delay |
| D. | wait |
| Answer» B. condition | |
| 514. |
The input overrides the input |
| A. | asynchronous , synchronous |
| B. | synchronous, asynchronou s |
| C. | preset input (pre), clear input (clr) |
| D. | clear input (clr), preset input (pre) |
| Answer» A. asynchronous , synchronous | |
| 515. |
A decade counter is . |
| A. | mod-3 counter |
| B. | mod-5 counter |
| C. | mod-8 counter |
| D. | mod-10 counter |
| Answer» D. mod-10 counter | |
| 516. |
In asynchronous transmission when the transmission line is idle, |
| A. | it is set to logic low |
| B. | it is set to logic high |
| C. | remains in previous state |
| D. | state of transmissi on line is not used to start transmissi on |
| Answer» B. it is set to logic high | |
| 517. |
A Nibble consists of bits |
| A. | 2 |
| B. | 4 |
| C. | 8 |
| D. | 16 |
| Answer» B. 4 | |
| 518. |
The output of this circuit is always . |
| A. | 1 |
| B. | 0 |
| C. | a |
| D. | abar |
| Answer» C. a | |
| 519. |
Excess-8 code assigns to “-8” |
| A. | 1110 |
| B. | 1100 |
| C. | 1000 |
| D. | 0 |
| Answer» D. 0 | |
| 520. |
The voltage gain of the Inverting Amplifier is given by the relation |
| A. | vout / vin = - rf / ri |
| B. | vout / rf = - vin / ri |
| C. | rf / vin = - ri / vout |
| D. | rf / vin = ri / vout |
| Answer» A. vout / vin = - rf / ri | |
| 521. |
LUT is acronym for |
| A. | look up table |
| B. | local user terminal |
| C. | least upper time period |
| D. | none of given options |
| Answer» A. look up table | |
| 522. |
The three fundamental gates are |
| A. | and, nand, xor |
| B. | or, and, nand |
| C. | not, nor, xor |
| D. | not, or, and |
| Answer» D. not, or, and | |
| 523. |
Stack is an acronym for |
| A. | fifo memory |
| B. | lifo memory |
| C. | flash memory |
| D. | bust flash memory |
| Answer» B. lifo memory | |
| 524. |
is one of the examples of synchronous inputs. |
| A. | j-k input |
| B. | en input |
| C. | preset input (pre) |
| D. | clear input (clr) |
| Answer» A. j-k input | |
| 525. |
occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay |
| A. | race condition |
| B. | clock skew |
| C. | ripple effect |
| D. | none of given options |
| Answer» B. clock skew | |
| 526. |
Consider an up/down counter that counts between 0 and 15, if external input(X) is “0” the counter counts upward (0000 to 1111) and if external input (X) is “1” the counter counts downward (1111 to 0000), now suppose that the present state is “1100” and X=1, the next state of the counter will be |
| A. | 0 |
| B. | 1101 |
| C. | 1011 |
| D. | 1111 |
| Answer» C. 1011 | |
| 527. |
In a state diagram, the transition from a current state to the next state is determined by |
| A. | current state and the inputs |
| B. | current state and outputs |
| C. | previous state and inputs |
| D. | previous state and outputs |
| Answer» A. current state and the inputs | |
| 528. |
is used to simplify the circuit that determines the next state. |
| A. | state diagram |
| B. | next state table |
| C. | state reduction |
| D. | state assignmen t |
| Answer» D. state assignmen t | |
| 529. |
Assume that a 4-bit serial in/serial out shift register is initially clear. We wish to store the nibble 1100. What will be the 4-bit pattern after the second clock pulse? (Right-most bit first.) |
| A. | 1100 |
| B. | 11 |
| C. | 0 |
| D. | 1111 |
| Answer» C. 0 | |
| 530. |
The diagram given below represents |
| A. | demorgans law |
| B. | associative law |
| C. | product of sum form |
| D. | sum of product form |
| Answer» D. sum of product form | |
| 531. |
The operation of J-K flip-flop is similar to that of the SR flip-flop except that the J-K flip-flop |
| A. | doesn’t have an invalid state |
| B. | sets to clear when both j = 0 and k = 0 |
| C. | it does not show transition on change in pulse |
| D. | it does not accept asynchron ous inputs |
| Answer» A. doesn’t have an invalid state | |
| 532. |
A multiplexer with a register circuit converts |
| A. | serial data to parallel |
| B. | parallel data to serial |
| C. | serial data to serial |
| D. | parallel data to parallel |
| Answer» B. parallel data to serial | |
| 533. |
A GAL is essentially a . |
| A. | non- reprogrammab le pal |
| B. | pal that is programmed only by the manufacture r |
| C. | very large pal |
| D. | reprogra mmable pal |
| Answer» D. reprogra mmable pal | |
| 534. |
in , all the columns in the same row are either read or written. |
| A. | sequential access |
| B. | mos access |
| C. | fast mode page access |
| D. | none of given options |
| Answer» C. fast mode page access | |
| 535. |
How many flip-flops are required to produce a divide-by-32 device? |
| A. | 2 |
| B. | 5 |
| C. | 6 |
| D. | 4 |
| Answer» B. 5 | |
| 536. |
A reduced state table has 18 rows. The minimum number of flip flops needed to implement the sequential machine is |
| A. | 18 |
| B. | 9 |
| C. | 5 |
| D. | 4 |
| Answer» C. 5 | |
| 537. |
Advantage of synchronous sequential circuits over asynchronous ones is |
| A. | faster operation |
| B. | ease of avoiding problems due to hazard |
| C. | lower hardware requirement |
| D. | better noise immunity |
| Answer» A. faster operation | |
| 538. |
The characteristic equation of a JK flip flop is |
| A. | qn+1=j.qn+k.q n |
| B. | qn+1=j.q’n+ k’.qn |
| C. | qn+1=qnj.k |
| D. | qn+1=(j+k )qn |
| Answer» B. qn+1=j.q’n+ k’.qn | |
| 539. |
WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO ------- |
| A. | the flop- flop is triggered |
| B. | q=0 and q‟=1 |
| C. | q=1 and q‟=0 |
| D. | the output of flip- flop remains unchang ed |
| Answer» D. the output of flip- flop remains unchang ed | |
| 540. |
In Q output of the last flip-flop of the shift register is connected to the data input of the first
|
| A. | moore machine |
| B. | meally machine |
| C. | johnson counter |
| D. | ring counter |
| Answer» D. ring counter | |
| 541. |
5-BIT JOHNSON COUNTER SEQUENCES THROUGH STATES |
| A. | 7 |
| B. | 10 |
| C. | 32 |
| D. | 25 |
| Answer» B. 10 | |
| 542. |
A 8-bit serial in / parallel out shift register contains the value “8”, clock signal(s) will be required to shift the value completely out of the register. |
| A. | 1 |
| B. | 2 |
| C. | 4 |
| D. | 8 |
| Answer» D. 8 | |
| 543. |
AT T0 THE VALUE STORED IN A 4-BIT LEFT SHIFT WAS “1”. WHAT WILL BE THE VALUE OF REGISTER AFTER THREE CLOCK PULSES? |
| A. | 2 |
| B. | 4 |
| C. | 6 |
| D. | 8 |
| Answer» D. 8 | |
| 544. |
The alternate solution for a multiplexer and a register circuit is |
| A. | parallel in / serial out shift register |
| B. | serial in / parallel out shift register |
| C. | parallel in / parallel out shift register |
| D. | serial in / serial out shift register |
| Answer» A. parallel in / serial out shift register | |
| 545. |
A multiplexer with a register circuit converts |
| A. | serial data to parallel |
| B. | parallel data to serial |
| C. | serial data to serial |
| D. | parallel data to parallel |
| Answer» B. parallel data to serial | |
| 546. |
A synchronous decade counter will have flip-flops |
| A. | 3 |
| B. | 4 |
| C. | 7 |
| D. | 10 |
| Answer» B. 4 | |
| 547. |
In outputs depend only on the current state. |
| A. | mealy machine |
| B. | moore machine |
| C. | state reduction table |
| D. | state assignmen t table |
| Answer» B. moore machine | |
| 548. |
Given the state diagram of an up/down counter, we can find |
| A. | the next state of a given present state |
| B. | the previous state of a given present state |
| C. | both the next and previous states of a given state |
| D. | the state diagram shows only the inputs/out puts of a given states |
| Answer» A. the next state of a given present state | |
| 549. |
THE HOURS COUNTER IS IMPLEMENTED USING |
| A. | only a single mod- 12 counter is required |
| B. | mod-10 and mod-6 counters |
| C. | mod-10 and mod-2 counters |
| D. | a single decade counter and a flip-flop |
| Answer» D. a single decade counter and a flip-flop | |
| 550. |
The design and implementation of synchronous counters start from |
| A. | truth table |
| B. | k-map |
| C. | state table |
| D. | state diagram |
| Answer» D. state diagram | |
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