McqMate
These multiple-choice questions (MCQs) are designed to enhance your knowledge and understanding in the following areas: Computer Science Engineering (CSE) , Electronics and Telecommunication Engineering [ENTC] .
| 551. |
THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A |
| A. | gated flip- flops |
| B. | pulse triggered flip-flops |
| C. | positive- edge triggered flip-flops |
| D. | negative -edge triggere d flip- flops |
| Answer» D. negative -edge triggere d flip- flops | |
| 552. |
A positive edge-triggered flip-flop changes its state when |
| A. | low-to-high transition of clock |
| B. | high-to-low transition of clock |
| C. | enable input (en) is set |
| D. | preset input (pre) is set |
| Answer» A. low-to-high transition of clock | |
| 553. |
Flip flops are also called |
| A. | bi-stable dualvibrators |
| B. | bi-stable transformer |
| C. | bi-stable multivibrator s |
| D. | bi-stable singlevibra tors |
| Answer» C. bi-stable multivibrator s | |
| 554. |
A FIELD-PROGRAMMABLE LOGIC ARRAY CAN BE PROGRAMMED BY THE USER AND NOT BY THE MANUFACTURER. |
| A. | true |
| B. | false |
| Answer» A. true | |
| 555. |
THE FOUR OUTPUTS OF TWO 4-INPUT MULTIPLEXERS, CONNECTED TO FORM A 16-INPUT
|
| A. | and |
| B. | or |
| C. | nand |
| D. | xor |
| Answer» B. or | |
| 556. |
A particular half adder has |
| A. | 2 inputs and 1 output |
| B. | 2 inputs and 2 output |
| C. | 3 inputs and 1 output |
| D. | 3 inputs and 2 output |
| Answer» B. 2 inputs and 2 output | |
| 557. |
A full-adder has a Cin = 0. What are the sum (<PRIVATE "TYPE=PICT;ALT=sigma"> ) and the carry (Cout) when A = 1 and B = 1? |
| A. | = 0, cout = 0 |
| B. | = 0, cout = 1 |
| C. | = 1, cout = 0 |
| D. | = 1, cout = 1 |
| Answer» B. = 0, cout = 1 | |
| 558. |
The sequence of states that are implemented by a n-bit Johnson counter is |
| A. | n+2 (n plus 2) |
| B. | 2n (n multiplied by 2) |
| C. | 2n (2 raise to power n) |
| D. | n2 (n raise to power 2) |
| Answer» B. 2n (n multiplied by 2) | |
| 559. |
A GAL is essentially a . |
| A. | non- reprogrammab le pal |
| B. | pal that is programmed only by the manufacture r |
| C. | very large pal |
| D. | reprogra mmable pal |
| Answer» D. reprogra mmable pal | |
| 560. |
The alternate solution for a demultiplexer-register combination circuit is |
| A. | parallel in / serial out shift register |
| B. | serial in / parallel out shift register |
| C. | parallel in / parallel out shift register |
| D. | serial in / serial out shift register |
| Answer» B. serial in / parallel out shift register | |
| 561. |
A transparent mode means |
| A. | the changes in the data at the inputs of the latch are seen at the output |
| B. | the changes in the data at the inputs of the latch are not seen at the output |
| C. | propagation delay is zero (output is immediately changed when clock signal is applied) |
| D. | input hold time is zero (no need to maintain input after clock transition) |
| Answer» A. the changes in the data at the inputs of the latch are seen at the output | |
| 562. |
occurs when the same clock signal arrives at different times at different clock inputs due to propagation delay. |
| A. | race condition |
| B. | clock skew |
| C. | ripple effect |
| D. | none of given options |
| Answer» B. clock skew | |
| 563. |
is one of the examples of asynchronous inputs. |
| A. | j-k input |
| B. | s-r input |
| C. | d input |
| D. | clear input (clr) |
| Answer» D. clear input (clr) | |
| 564. |
Bi-stable devices remain in either of their states unless the inputs force the device to switch its state |
| A. | ten |
| B. | eight |
| C. | three |
| D. | two |
| Answer» D. two | |
| 565. |
RCO Stands for |
| A. | reconfiguratio n counter output |
| B. | reconfigurati on clock output |
| C. | ripple counter output |
| D. | ripple clock output |
| Answer» D. ripple clock output | |
| 566. |
A positive edge-triggered flip-flop changes its state when |
| A. | low-to-high transition of clock |
| B. | high-to-low transition of clock |
| C. | enable input (en) is set |
| D. | preset input (pre) is set |
| Answer» A. low-to-high transition of clock | |
| 567. |
The low to high or high to low transition of the clock is considered to be a(n) |
| A. | state |
| B. | edge |
| C. | trigger |
| D. | one-shot |
| Answer» B. edge | |
| 568. |
In asynchronous digital systems all the circuits change their state with respect to a common clock |
| A. | true |
| B. | false |
| Answer» B. false | |
| 569. |
If the S and R inputs of the gated S-R latch are connected together using a gate then there is only a single input to the latch. The input is represented by D instead of S or R (A gated D-Latch) |
| A. | and |
| B. | or |
| C. | not |
| D. | xor |
| Answer» C. not | |
| 570. |
If S=1 and R=0, then Q(t+1) = for positive edge triggered flip-flop |
| A. | 0 |
| B. | 1 |
| C. | invalid |
| D. | input is invalid |
| Answer» B. 1 | |
| 571. |
3-to-8 decoder can be used to implement Standard SOP and POS Boolean expressions |
| A. | true |
| B. | false |
| Answer» A. true | |
| 572. |
The Encoder is used as a keypad encoder. |
| A. | 2-to-8 encoder |
| B. | 4-to-16 encoder |
| C. | bcd-to- decimal |
| D. | decimal- to-bcd priority |
| Answer» D. decimal- to-bcd priority | |
| 573. |
The simplest and most commonly used Decoders are the Decoders |
| A. | n to 2n |
| B. | (n-1) to 2n |
| C. | (n-1) to (2n- 1) |
| D. | n to 2n-1 |
| Answer» A. n to 2n | |
| 574. |
A Karnaugh map is similar to a truth table because it presents all the possible values of input variables and the resulting output of each value. |
| A. | true |
| B. | false |
| Answer» A. true | |
| 575. |
The decimal “17” in BCD will be represented as 10001(right opt is not given) |
| A. | 11101 |
| B. | 11011 |
| C. | 10111 |
| D. | 11110 |
| Answer» C. 10111 | |
| 576. |
Q2 :=Q1 OR X OR Q3 The above ABEL expression will be |
| A. | q2:= q1 $ x $ q3 |
| B. | q2:= q1 # x # q3 |
| C. | q2:= q1 & x & q3 |
| D. | q2:= q1 ! x ! q3 |
| Answer» B. q2:= q1 # x # q3 | |
| 577. |
Above is the circuit diagram of |
| A. | asynchronous up-counter |
| B. | asynchronou s down- counter |
| C. | synchronous up-counter |
| D. | synchrono us down- counter |
| Answer» A. asynchronous up-counter | |
| 578. |
The high density FLASH memory cell is implemented using |
| A. | 1 floating-gate mos transistor |
| B. | 2 floating- gate mos transistors |
| C. | 4 floating- gate mos transistors |
| D. | 6 floating- gate mos transistors |
| Answer» A. 1 floating-gate mos transistor | |
| 579. |
A bidirectional 4-bit shift register is storing the nibble 1110. Its input is LOW. The nibble 0111 is waiting to be entered on the serial data-input line. After two clock pulses, the shift register is storing . |
| A. | 1110 |
| B. | 111 |
| C. | 1000 |
| D. | 1001 |
| Answer» D. 1001 | |
| 580. |
At T0 the value stored in a 4-bit left shift was “1”. What will be the value of register after three clock pulses? |
| A. | 2 |
| B. | 4 |
| C. | 6 |
| D. | 8 |
| Answer» D. 8 | |
| 581. |
A multiplexer with a register circuit converts |
| A. | serial data to parallel |
| B. | parallel data to serial |
| C. | serial data to serial |
| D. | parallel data to parallel |
| Answer» B. parallel data to serial | |
| 582. |
In outputs depend only on the combination of current state and inputs |
| A. | mealy machine |
| B. | moore machine |
| C. | state reduction table |
| D. | state assignmen t table |
| Answer» A. mealy machine | |
| 583. |
The input overrides the input |
| A. | asynchronous, synchronous |
| B. | synchronous, asynchronou s |
| C. | preset input (pre), clear input (clr) |
| D. | clear input (clr), preset input (pre) |
| Answer» A. asynchronous, synchronous | |
| 584. |
For a gated D-Latch if EN=1 and D=1 then Q(t+1) = |
| A. | 0 |
| B. | 1 |
| C. | q(t) |
| D. | invalid |
| Answer» B. 1 | |
| 585. |
If S=1 and R=1, then Q(t+1) = for negative edge triggered flip- flop |
| A. | 0 |
| B. | 1 |
| C. | invalid |
| D. | input is invalid |
| Answer» C. invalid | |
| 586. |
The sequence of states that are implemented by a n-bit Johnson counter is |
| A. | n+2 |
| B. | 2n |
| C. | 2 raise to power n |
| D. | n raise to power 2 |
| Answer» B. 2n | |
| 587. |
The alternate solution for a multiplexer and a register circuit is |
| A. | parallel in / serial out shift register |
| B. | serial in / parallel out shift register |
| C. | parallel in / parallel out shift register |
| D. | serial in / serial out shift register |
| Answer» A. parallel in / serial out shift register | |
| 588. |
THE GLITCHES DUE TO RACE CONDITION CAN BE AVOIDED BY USING A |
| A. | gated flip- flops |
| B. | pulse triggered flip-flops |
| C. | positive- edge triggered flip-flops |
| D. | negative -edge triggere d flip- flops |
| Answer» D. negative -edge triggere d flip- flops | |
| 589. |
Flip flops are also called |
| A. | bi-stable dualvibrators |
| B. | bi-stable transformer |
| C. | bi-stable multivibrator s |
| D. | bi-stable singlevibra tors |
| Answer» C. bi-stable multivibrator s | |
| 590. |
A transparent mode means |
| A. | the changes in the data at the inputs of the latch are seen at the output |
| B. | the changes in the data at the inputs of the latch are not seen at the output |
| C. | propagation delay is zero (output is immediately changed when clock signal is applied) |
| D. | input hold time is zero (no need to maintain input after clock transition) |
| Answer» A. the changes in the data at the inputs of the latch are seen at the output | |
| 591. |
Given the state diagram of an up/down counter, we can find |
| A. | the next state of a given present state |
| B. | the previous state of a given present state |
| C. | both the next and previous states of a given state |
| D. | the state diagram shows only the inputs/out puts of a given states |
| Answer» A. the next state of a given present state | |
| 592. |
In Q output of the last flip-flop of the shift register is connected to the data input of the first flip-flop of the shift register. |
| A. | moore machine |
| B. | meally machine |
| C. | johnson counter |
| D. | ring counter |
| Answer» D. ring counter | |
| 593. |
status. |
| A. | 3 |
| B. | 7 |
| C. | 8 |
| D. | 15 |
| Answer» C. 8 | |
| 594. |
We have a digital circuit. Different parts of circuit operate at different clock frequencies (4MHZ, 2MHZ and 1MHZ), but we have a single clock source having a fix clock frequency (4MHZ), we can get help by |
| A. | using s-r flop- flop |
| B. | d-flipflop |
| C. | j-k flip-flop |
| D. | t-flip-flop |
| Answer» C. j-k flip-flop | |
| 595. |
If S=1 and R=1, then Q(t+1) = for negative edge triggered flip- flop |
| A. | 0 |
| B. | 1 |
| C. | invalid |
| D. | input is invalid |
| Answer» C. invalid | |
| 596. |
WHEN BOTH THE INPUTS OF EDGE-TRIGGERED J-K FLOP-FLOP ARE SET TO LOGIC ZERO |
| A. | the flop- flop is triggered |
| B. | q=0 and q‟=1 |
| C. | q=1 and q’=0 |
| D. | the output of flip- flop remains unchang ed |
| Answer» C. q=1 and q’=0 | |
| 597. |
If an S-R latch has a 1 on the S input and a 0 on the R input and then the S input goes to 0, the latch will be |
| A. | set |
| B. | reset |
| C. | invalid |
| D. | clear |
| Answer» A. set | |
| 598. |
For a positive edge-triggered J-K flip-flop with both J and K HIGH, the outputs will if the clock goes HIGH. |
| A. | toggle |
| B. | set |
| C. | reset |
| D. | not change |
| Answer» A. toggle | |
| 599. |
What is the difference between a D latch and a D flip-flop? |
| A. | the d latch has a clock input. |
| B. | the d flip- flop has an enable input. |
| C. | the d latch is used for faster operation. |
| D. | the d flip- flop has a clock input. |
| Answer» D. the d flip- flop has a clock input. | |
| 600. |
A frequency counter |
| A. | counts pulse width |
| B. | counts no. of clock pulses in 1 second |
| C. | counts high and low range of given clock pulse |
| D. | none of given options |
| Answer» B. counts no. of clock pulses in 1 second | |
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